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| 1 of 40 semtech proprietary & confidential GS3140 final data sheet rev.1 pds-060939 may 2015 GS3140 multi-rate adaptive 3g sdi equalizer www.semtech.com key features ? multi-standard operation at rates between 1mb/s and 2.97gb/s ? smpte st 424, smpte st 292 and smpte st 259 compliant ? aes10 (madi) compatible ? industry leading cable reach, with automatic cable equalization for different lengths of cable ? performance optimized for 125mb/s, 270mb/s, 1.485gb/s, and 2.97gb/s. typical equalized length of belden 1694a cable up to: ? 200m at 2.97gb/s ? 280m at 1.485gb/s ? 500m at 270mb/s ? 1.8v core power supply ? typical power consumption of 84mw when dc-coupled at 1.2v with output_swing = 0011 b (see table 4-2 ) ? ultra-low power mode for shorter cable reach applications ? upstream launch swing co mpensation from 250mv ppd to 1v ppd in approximately 50mv ppd steps (default 750mv ppd ) ? auto/manual bypass (useful for low data rates with slow rise/fall times) ? robust, noise-immune signal detection with squelch threshold adjustment ? auto/manual control of sl eep/mute/disable output modes ? data rate detection and indication ? GS3140 final data sheet rev.1 pds-060939 may 2015 2 of 40 semtech proprietary & confidential www.semtech.com the differential output can be dc-coupled to semtechs reclockers and cable drivers, as well as industry-standard +1.2v, +1.8v and +2.5v cml logic by changing the voltage applied to the vcc_o pin. the GS3140 also features programmable output de-emphasis with eight user-selectable operating levels to support long pcb traces at th e output of the device. the output swing can be programm ed, via the user interface, from approximately 250mv ppd to 1v ppd in 50mv ppd steps. the device comes in a 16 -pin, 4mm x 4mm qfnCcol package. power consumption of the gs31 40 is typically 84mw when dc-coupled to a +1.2v termination voltage with output_swing = 0011 b (see table 4-2 ). the GS3140 is pb-free, and the encapsulation compound does not contain halogenated flame retardant. this component and all homo geneous subcomponents are rohs compliant. GS3140 functional block diagram control and status equalizer dc restore output trace driver agc vcc_a sdi vee_a agc vee_o ddo vcc_o sclk sdin sdout sdi agc ddo cs int vcc_d GS3140 final data sheet rev.1 pds-060939 may 2015 3 of 40 semtech proprietary & confidential www.semtech.com revision history contents 1. pin out..................................................................................................................... ............................................5 1.1 GS3140 pin assignment ..................................................................................................... ..............5 1.2 GS3140 pin descriptions ................................................................................................... ...............5 2. electrical characteristics.................................................................................................. ..............................7 2.1 absolute maximum ratings .................................................................................................. .........7 2.2 dc electrical characteristics ............................................................................................. ..............7 2.3 ac electrical characteristics ............................................................................................. ...............9 3. input/output circuits....................................................................................................... ........................... 11 4. detailed description........................................................................................................ ............................ 12 4.1 serial digital inputs (sdi/sdi) ........................................................................................... ........... 12 4.1.1 upstream launch swing compensation.................................................................... 12 4.2 automatic (adaptive) cable equalization .............................................................................. 12 4.3 cable length indication ................................................................................................... ............. 13 4.4 programmable squelch threshold ........................................................................................... 1 3 4.5 loss of signal (los) ...................................................................................................... ................... 14 4.5.1 programmable los filter ................................................................................................. 1 4 4.6 rate detection ............................................................................................................ ...................... 15 4.7 interrupt (int)/ status output ............................................................................................ ........ 15 4.8 power modes ............................................................................................................... ..................... 15 4.8.1 bypass................................................................................................................... ................... 15 4.8.2 sleep.................................................................................................................... ..................... 15 4.8.3 mute ..................................................................................................................... .................... 16 4.8.4 sleep-mute............................................................................................................... .............. 16 4.8.5 output disable ........................................................................................................... .......... 16 4.9 serial digital output (ddo/ddo) ........................................................................................... ... 16 4.9.1 adjustable output swing and de-emphasis............................................................. 17 4.9.2 output common mode voltage.................................................................................... 18 4.10 device reset ............................................................................................................. ....................... 19 4.11 gennum serial peripher al interface (gspi) .......................................................................... 19 4.11.1 cs pin........................................................................................................................... .......... 19 4.11.2 sdin pin................................................................................................................ ................ 20 4.11.3 sdout pin ............................................................................................................... ............ 20 4.11.4 sclk pin................................................................................................................ ................ 22 4.11.5 command word description........................................................................................ 22 version eco pcn date changes and/or modifications 1 025657 may 2015 converted document from draft data sheet to final data sheet. 0 024058 january 2015 new document. 4 of 40 semtech proprietary & confidential GS3140 final data sheet rev.1 pds-060939 may 2015 www.semtech.com 4.11.6 gspi transaction timing................................................................................................. 24 4.11.7 single read/write access............................................................................................... 2 5 4.11.8 auto-increment read/write access ........................................................................... 27 4.11.9 default gspi operation.................................................................................................. .28 4.11.10 setting a device unit address ................................................................................... 29 5. host interface register map................................................................................................. ..................... 30 6. application information..................................................................................................... ........................ 36 6.1 typical application circuit ............................................................................................... ............ 36 7. package & ordering information .............................................................................................. .............. 37 7.1 package dimensions ........................................................................................................ .............. 37 7.2 packaging data ............................................................................................................ ..................... 38 7.3 recommended pcb footprint ................................................................................................. ... 38 7.4 marking diagram ........................................................................................................... .................. 39 7.5 solder reflow profiles .................................................................................................... ................ 39 7.6 ordering information ...................................................................................................... ............... 39 GS3140 final data sheet rev.1 pds-060939 may 2015 5 of 40 semtech proprietary & confidential www.semtech.com 1. pin out 1.1 GS3140 pin assignment figure 1-1: GS3140 pin out 1.2 GS3140 pin descriptions GS3140 16-pin qfn?col (top view) sclk agc vcc_d sdout int sdin 5678 16 15 14 13 agc vee_a vcc_a sdi 1 2 3 4 sdi vcc_o ddo ddo vee_o 12 11 10 9 cs table 1-1: GS3140 pin descriptions pin number name type description 1 vcc_a power most positive power supply connectio n for the input buffer and core. connect to 1.8v. 2, 3 sdi, sdi input serial digital differential input. 4 vee_a power most negative power supply connection for the input buffer and core. connect to gnd. 5, 6 agc, agc analog i/o external automatic gain control capacitor. 7 sdin digital input host interface serial data input. 8 sclk digital input host interface serial clock input. 9 vee_o power most negative power supply connection for the output buffers, digital io and digital circuits. connect to gnd. 10, 11 ddo, ddo output serial digital differential output. 12 vcc_o power most positive power supply conne ction for the output buffer. connect to 1.2v - 2.5v. GS3140 final data sheet rev.1 pds-060939 may 2015 6 of 40 semtech proprietary & confidential www.semtech.com 13 vcc_d power most positive power supply connection for the digital io and the digital circuits. connect to 1.8v. 14 sdout digital output host interface serial data output 15 cs digital input host interface chip select (active low) 16 int digital output interrupt, programmable status pin. default is loss of signal (los) table 1-1: GS3140 pin descri ptions (continued) pin number name type description GS3140 final data sheet rev.1 pds-060939 may 2015 7 of 40 semtech proprietary & confidential www.semtech.com 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics table 2-1: absolute maximum ratings parameter value supply voltage - core (vcc_a and vcc_d) -0.5v to +2.1v supply voltage - output driver (vcc_o) -0.5v to +2.8v input esd voltage 3kv hbm storage temperature range (t s ) -50c to 125c input voltage range (any input) -0.3 to (vcc_a +0.3)v solder reflow temperature 260c note: absolute maximum ratings are those values beyond which damage may occur. functional operation outside of the ranges shown in the ac/dc electrical characteristics tables is not guaranteed. table 2-2: dc electrical characteristics v cc_a ,v cc_d, v cc_o = +1.8v 5%, t a = -40c to +85c, unless otherwise shown parameter symbol conditions min typ max units notes supply voltage - core v cc_a ,v cc_d 1.710 1.8 1.890 v supply voltage - output driver v cc_o 1.140 2.625 v power p d v cc_o = 1.2v output_swing = 0011 b 85 135 mw 1 , 2 v cc_o = 1.2v output_swing = 1011 b 95 148 mw 1 , 2 v cc_o = 1.8v output_swing = 0011 b 90 143 mw 1 , 2 v cc_o = 1.8v output_swing = 1011 b 104 162 mw 1 , 2 v cc_o = 2.5v output_swing = 0011 b 96 152 mw 1 , 2 v cc_o = 2.5v output_swing = 1011 b 116 178 mw 1 , 2 GS3140 final data sheet rev.1 pds-060939 may 2015 8 of 40 semtech proprietary & confidential www.semtech.com power consumption C bypass mode p d_bypass 58 88 mw power consumption C output mute p d_mute 83 127 mw power consumption C output disable p d_disable 70 114 mw power consumption C sleep-mute p d_sleep_mute 49mw power consumption C sleep p d_sleep 11 27 mw supply current C core i dd_a v cc_a = 1.8v 3756ma 1 , 3 supply current - digital i dd_d v cc_d = 1.8v 57.5ma supply current - output driver i dd_o v dd_o = +1.2v to +2.5v output_swing = 0011 b 812ma 1 , 2 v dd_o = +1.2v to +2.5v output_swing = 1011 b 1622ma 1 , 2 serial input common mode voltage v cmin 1.4 1.6 v serial output common mode voltage v cmout see section 4.9.2 input voltage - digital pins (cs , sdin, sclk) v ih 0.65* vdd_dig vdd_dig v v il 0 0.35* vdd_dig v output voltage - digital pins (int, sdout) v oh i oh = -2ma vdd_dig C 0.45 v v ol i oh = 2ma 0.45v notes: 1. de-emphasis off. 2. see table 4-2 for all the output swing settings. 3. with de-emphasis enabled, add a typical 4ma. table 2-2: dc electrical characteristics (continued) v cc_a ,v cc_d, v cc_o = +1.8v 5%, t a = -40c to +85c, unless otherwise shown parameter symbol conditions min typ max units notes GS3140 final data sheet rev.1 pds-060939 may 2015 9 of 40 semtech proprietary & confidential www.semtech.com 2.3 ac electrical characteristics table 2-3: ac electrical characteristics v cc_a ,v cc_d, v cc_o = +1.8v 5%, t a = -40c to +85c, unless otherwise shown parameter symbol conditions min typ max units notes serial input data rate dr ddo 1 2970 mb/s input voltage swing v sdi differential, 1.485gb/s 720 800 960 mv ppd differential, 125mb/s, 270mb/s, and 2.97gb/s 720 800 880 mv ppd input sensitivity 16 increments of approximately 50mv ppd 250 1000 mv ppd 1 output voltage swing v ddo output_swing = 0100 b 345 410 475 mv ppd 2 output_swing = 1100 b 665 800 935 mv ppd 2 output jitter at various cable lengths and data rates j pp 2.97gb/s belden 1694a: 0-120m, -20c to +70c 0.2 0.25 ui 3 , 4 , 5 2.97gb/s belden 1694a: 120-180m, -20c to +70c 0.40.5ui 3 , 4 , 5 2.97gb/s belden 1694a: 180-200m, -20c to +70c 0.4 ui 3 , 4 , 5 1.485gb/s belden 1694a: 0-180m 0.15 0.25 ui 1.485gb/s belden 1694a: 180-240m 0.30.4ui 1.485gb/s belden 1694a: 240-280m 0.35 0.45 ui 270mb/s belden 1694a: 0-300m 0.10.2ui 270mb/s belden 1694a: 300-350m 0.2 0.3 270mb/s belden 1694a: 350-450m 0.30.4ui 270mb/s belden 1694a: 450-500m 0.3 ui 125mb/s belden 1694a: 0-200m 0.1ui output rise/fall time 2.97gb/s and 1.485gb/s 20% - 80% 4590ps 270mb/s 20% - 80% 50200ps mismatch in rise/fall time 2.97gb/s and 1.485gb/s 30 ps 270mb/s 50 ps GS3140 final data sheet rev.1 pds-060939 may 2015 10 of 40 semtech proprietary & confidential www.semtech.com duty cycle distortion 2.97gb/s and 1.485gb/s 65 ps 270mb/s 65 ps input resistance single ended 3.1 k input capacitance single ended 1.1 pf output resistance single ended 50 input capacitance - digital pins (cs , sdin, sclk) 0.8pf output capacitance - digital pins (int, sdout) 1.0pf input return loss 1.485ghz to 2.97ghz 10 db 6 5mhz to 1.485ghz 15 db 6 note: 1. for input swing < 720mv ppd , the overall cable reach may be reduced. 2. see table 4-2 for all the output swing settings. 3. for -40 c to -20 c operation at less than 40m of belden 1694a cable, add 0.1ui to jitter specification. 4. for -40 c to -20 c operation at greater than 40m of belden 1694a cable, jitter specification does not change. 5. operation from +70 c to +85 c is not supported. 6. using semtechs recommended application circuit and design guides. table 2-3: ac electrical ch aracteristics (continued) v cc_a ,v cc_d, v cc_o = +1.8v 5%, t a = -40c to +85c, unless otherwise shown parameter symbol conditions min typ max units notes GS3140 final data sheet rev.1 pds-060939 may 2015 11 of 40 semtech proprietary & confidential www.semtech.com 3. input/output circuits figure 3-1: serial data input figure 3-2: agc, agc 3.5k rc sdi sdi rc 2k 1k 2k vcc_a vcc_a vcc_a 500pf agc 250 vcc_a agc vcc_a 250 50 50 ddo ddo vcc_o vcc_o vcc_o 100k vcc_d vcc_d sdin, sclk 100k vcc_d vcc_d cs vcc_d sdout, int vcc_d vcc_d GS3140 final data sheet rev.1 pds-060939 may 2015 12 of 40 semtech proprietary & confidential www.semtech.com 4. detailed description the GS3140 is a high-speed bicmos ic designed to equalize serial digital signals. the GS3140 can equalize 3g sdi, hd-sdi, sd-sdi and aes10 serial digital signals, and will typically equalize up to 200m at 2.97gb/s, 280m at 1.485gb/s, 500m at 270mb/s and 200m at 125mb/s. when dc coupling the output of a device to a 1.2v cml load, the GS3140 typically consumes 84mw of power with a 400 mv ppd output swing. 4.1 serial digital inputs (sdi/ sdi ) the GS3140 has a high-impedance input buffer. the received serial data signal can be connected to the input pins (sdi/sdi ) in either a differential or single-ended configuration. the input circuit is self-biasing to allow fo r simple ac-coupling of input signals to the device. 4.1.1 upstream launch swing compensation the GS3140 has automatic gain control that is based on the assumption that the cable driver in the upstream device is smpte compliant and has a launch swing of 800mv ppd 10%. when the source amplitude is known to be non-smpte compliant, a compensation adjustment can be made. the GS3140 can adjust for nominal launch swings between 250mv ppd to 1000mv ppd , in approximately 50mv ppd increments. upstream launch swing compensation can be adjusted usin g the launch_swing_compensation bits in eq_conf_reg_2 register. the default value is 800mv ppd (1011 b ). 4.2 automatic (adaptive) cable equalization the GS3140 automatically adjust s its gain to equalize and re store signals received over different lengths of coaxial cable having loss characteristics similar to belden 8281 or 1694a. the device is designed to automatica lly equalize smpte sdi signal rates up to 2.97gb/s, dvb-asi signals at 270mb/s, and madi signals at 125mb/s. the GS3140 has the ability to limit the reach of the device to one of four values through its host interface. the default value is th e maximum range. the maximum range of the device is also a function of the detected data rate, so the maximum cable will not exceed the supported reac h for that rate. GS3140 final data sheet rev.1 pds-060939 may 2015 13 of 40 semtech proprietary & confidential www.semtech.com 4.3 cable length indication the GS3140 reports the input signal stre ngth through the cable_length_indicator bits in the status_reg_0 re gister, accessible through the device's host interface. the cable length indication (cli) is a simple, numeric value in the range from 0 h to ef h . this number can be approximated as a cable length in meters by applying one of the cable scaling factors shown in table 4-1 below for some commonl y used coaxial cables. the cli readout value has a multiplication resolution of 1 between 0 h and 7f h . in the range from 80 h to ef h the measurement reso lution of cli is reduced, and cli value increments by a multiple of 3. note: any additional loss due to other transmission line elements (such as patch panels, barrels, extra connectors, etc.), also translates to an equivalent cable length based on the cable scaling factor. 4.4 programmable squelch threshold the GS3140 features a programmable squelch threshold, set through the device's host interface. it impacts loss of si gnal (los) status. as shown in figure 4-1 , squelch only affects the los status wh en bits auto_bypass, by pass, and sleep[1:0] in eq_conf_reg_0 are all 0. the device continually compares the strength of the input signal as set in the cable_length_indicator bi ts in the status_reg_0 register to the squelch threshold set by the sque lch_threshold bits in the eq_conf_reg_1 register. when the value reported by the cable_length_indicator bits exceeds the value programmed by the squelch_threshold bits by 3 or more, the loss of signal (los) status bit in the status_reg _0 register is set to 1. when the value reported by the cable_length_indicator bits falls below the value programmed by the squelch_threshold bits by 3 or more, the loss of signal (los) status bit in the status_reg _0 register is set to 0. this 2 hysteresis around the squelch_threshold setting avoids chattering of the los bit status for input signal streng ths right around th e threshold setting. by default, the squelc h threshold is set to the maximum possible level, and therefore squelch is disabled. table 4-1: cable length scaling factors cable type cli scaling factor belden 1694a 2.5 belden 8281 1.77 GS3140 final data sheet rev.1 pds-060939 may 2015 14 of 40 semtech proprietary & confidential www.semtech.com 4.5 loss of signal (los) the loss of signal (los) status indicates whether or not a si gnal that meets the devices programmed thresholds is present at its input. when los is de-asserted (set to 0), a supported input signal has been detected. figure 4-1 shows how los is derived. the los function continuously monitors conditions of the input signal. in sleep, auto-sleep, bypass or auto-by pass modes, this is limited to carrier detection. when los filter is disabled, los will be asserted (set to 1) no less than 10s and no longer than 40s after the loss of a valid input signal, and will be de-asserted (set to 0) no more than 5s after the conn ection of a valid input signal. los is available via a status bit in status_reg _0, and it is also available on the interrupt (int) status pin, as selected us ing the int_source_select bits in int_out_conf_reg_0 register accessible thro ugh the devices host interface. los is the default output from the int pin. 4.5.1 programmable los filter the los filter delays notification of the change in raw los until the new state persists contiguously for the programmed length of time. this increase s stability of los signalling. the los filter assertion an d de-assertion delays can be programmed through the GS3140 host interface. by default, the los filter is set to 51.8s assertion delay and 6.6ms de-assertion delay. the los assertion delay can be set in the range from 0ms to 6.6ms in increments of 25.9s. the los de-assertion delay can be set in the range of 0s to 1.7s in increments of 6.6ms. these parameters are accessible using the los_filter_set_delay and los_filter_clear_delay bits in los_filter_conf_reg_0 the use of these parameters can be disabled using the los_filter_disable bit in los_filter_conf_reg_1. figure 4-1 below shows the derivation of the los status indication, and how the los filter affects the output. figure 4-1: factors affecting the a ssertion of the los status parameter los filter raw los 1 0 los_filter_disable los (status parameter) los_filter_set_delay los_filter_clear_delay carrier detect set to 1 when any of the following: sleep, auto_sleep, bypass, auto bypass combination of carrier detect and squelch GS3140 final data sheet rev.1 pds-060939 may 2015 15 of 40 semtech proprietary & confidential www.semtech.com 4.6 rate detection the GS3140 will differentiate between 2.97gb/s, 1.485gb/s, 270mb/s, 125mb/s, and <125mb/s. the detected data rate is reported using the detected_input_rate bits in status_reg_0 accessible through the devices host interface. indication of the detected rate is also avai lable on the interrupt (int) status pin, as selected using the int_source_selec t and int_cd_mode_select bits in int_out_conf_reg_0 accessible thro ugh the devices host interface. 4.7 interrupt (int)/ status output the GS3140s programmable interrupt (int) pin flags internal states, or changes of state to the host system. the default function of this pin is loss of signal (los). other functions are programmed via the devices ho st interface. the additional functions include: ? rate change detection ? detection of a specific data rate or set of rates these functions are chosen using bits int_source_select, int_cd_mode_select, and data_rate_detection in the int_out_conf_reg_0 register. 4.8 power modes 4.8.1 bypass the GS3140 supports a mode of operation where the equalizer core and dc restoration stages are bypassed. this mode is cont rolled by the settings of the bypass and auto_bypass bits in eq_conf_ reg_0 of the host interface. no equalization or dc restoration occurs in bypass mode. these functions are disabled in order to reduce power consumption of the device for signals that do not require equalization and dc restoration. when the device is in bypass, the los continues to function based on carrier detect. in addition to manual-bypass, auto-bypass is also available. when the auto_bypass bit in eq_conf_reg_0 is set to 1, bypass is in itiated by detection of an input signal with a data rate below madi. 4.8.2 sleep the GS3140 features a sleep function that is controlled through the host interface. when the part is in sleep mode, only ca rrier based loss of si gnal (los) detection remains active. all other sections of the part are powered down. when in sleep mode, the part consumes 13mw of total power. GS3140 final data sheet rev.1 pds-060939 may 2015 16 of 40 semtech proprietary & confidential www.semtech.com when auto-sleep is selected, it is initiated by the assertion of los. normal operation, manual-sleep, and auto-sleep are controlled using the sleep bits in eq_conf_reg_0 accessed through the devices host interface. 4.8.3 mute the GS3140 features a mute fun ction, in which the two halv es of the output buffer are driven statically to opposing levels. one will be set to the level of v cc_o and the other will be set to v cc_o C swing amplitude (swing level se t in the output_swing bits of out_conf_reg_0). when auto-mute is selected, it is initiate d by the assertion of los. manual-mute and auto-mute are controlled using the mu te and auto_output_mute bits in out_conf_reg_1 accessed throug h the device's host interface. 4.8.4 sleep-mute by default, output drivers are powered down when the device is in sleep mode. however, the GS3140 also features another power saving sleep mode in which the output driver is muted (as described in section 4.8.3 ) instead. all the other blocks are configured similar to the description in section 4.8.2 . the purpose of this mode is to output a noise-immune static signal while the chip is sleeping. similar to sleep mode, both manual and automatic features are available. when mute_output_in_sleep bi t in eq_conf_reg_2 is set to 1, the output drivers will remain powered and enter mute whenever the device is in sleep. 4.8.5 output disable the GS3140 features a mode of operation in which the output buffer is disabled to save power, but all other parts of the chip remain active. this mode of operation consumes more po wer than sleep mode, but less power than normal operation. it facilitates faster return to normal operation than sleep mode when required, because all internal stages of the eq core are already ac tive in this mode. by default, if the device is not set to any other automatic power mode (auto-sleep, auto-mute, auto-sleep-mute), then the assertion of los wi ll initiate output disable mode. the output buffer will remain disabled until a signal is present. if there is a signal present, the outputs ma y still be manually disabled by setting the manual_output_disable bit in out_conf _reg_1 to 1, accessed through the devices host interface. 4.9 serial digital output (ddo/ ddo ) the output driver has a separate voltage supply (v cc_o ) which operates between 1.2v - 2.5v. the output buffer includes two on-chip 50 termination resistors. GS3140 final data sheet rev.1 pds-060939 may 2015 17 of 40 semtech proprietary & confidential www.semtech.com the output is compatible with industry standard pecl, lvpecl, lvds, and cml differential receivers when ac coupled using semtechs reco mmended application circuit. 4.9.1 adjustable output swing and de-emphasis the serial digital output swing is user-selectable from approximately 250mv ppd to 1v ppd in increments of 50mv ppd . for exact values see table 4-2 . to support driving long pcb traces, the GS3140 differential output buffer includes programmable de-emphasis with 8 operat ing levels between 0db - 18.1db. the de-emphasis delay can also be prog rammed to either 100ps or 200ps. a second set of de-emphasis le vel and delay values, specifically targeted for 2.97gb/s signals, can be selected either manually using the manual_deemphasis_select bit or automatically using the auto_deemphas is_enable bit in out_conf_reg_0 accessible through the de vice's host interface. table 4-2: serial digital output swing output_swing min typ max units 0000 b 190 230 270 mv 0001 b 230 275 320 mv 0010 b 275 325 375 mv 0011 b 310 370 430 mv 0100 b 345 410 475 mv 0101 b 390 460 530 mv 0110 b 435 510 585 mv 0111 b 480 560 640 mv 1000 b 515 605 695 mv 1001 b 555 655 755 mv 1010 b 590 705 820 mv 1011 b 630 755 880 mv 1100 b 665 800 935 mv 1101 b 695 840 985 mv 1110 b 745 890 1035 mv 1111 b 800 930 1060 mv GS3140 final data sheet rev.1 pds-060939 may 2015 18 of 40 semtech proprietary & confidential www.semtech.com 4.9.2 output common mode voltage the output common mode voltage level (v cmout ) is a function of the output voltage swing, the output dr iver supply voltage (v cc_o ) and how the transmission line is terminated. if the outputs are terminated through 50 resistors to a voltage v term equal to v cc_o , as shown in figure 4-2 below, the output common mode voltage is given by the foll owing expression: equation 4-1 if the differential outputs are terminated across a 100 resistor, as shown in figure 4-3 below, the output common mode voltage is given by the fo llowing expression: equation 4-2 table 4-3: de-emphasis levels de-emphasis level operating level units 000 b 0db 001 b 1.2 db 010 b 2.5 db 011 b 4.1 db 100 b 6.0 db 101 b 8.5 db 110 b 12.0 db 111 b 18.1 db v cmout v cc _ o v ddo 4 ----------------- - ? = v cmout v cc _ o v ddo 2 ----------------- - ? = figure 4-2: 50 termination to v term figure 4-3: 100 parallel output termination 50 50 ddo vcc_o 50 50 GS3140 v term v term 50 50 ddo 100 50 50 50 50 ddo vcc_o GS3140 ddo GS3140 final data sheet rev.1 pds-060939 may 2015 19 of 40 semtech proprietary & confidential www.semtech.com 4.10 device reset the GS3140 includes a reset function accessible via the device's host interface, which reverts all internal logic and register values to default. the device can be reset with a single write of ad h to the reset_control bits of reset_reg_0 register, which will assert an d de-assert the device reset within the duration of the gspi write access data word. the device can be placed and held in reset by writing aa h to the reset_control bits of reset_reg_0 register. subsequent writes of dd h to the reset_control bits will de-assert device reset. the current state of user-initiated device reset can be read from the reset_control bits of reset_reg_0 register. while in reset, host interface accesses to any other register wi ll not be functional and all logic and configuration registers will be in reset state. while in reset serial digital differential output be haviour is undefined. the digital logic and registers within the device will exit the reset state 40s after device reset is de-asserted. note: reset_reg_0 register writes do not support auto-increment mode. 4.11 gennum serial peripheral interface (gspi) the gennum serial peripheral interface (gspi) is comprised of a serial data input signal (sdin pin), serial data output signal (sdo ut pin), an active-low chip select (cs pin) and a burst clock (sclk pin). the GS3140 is a slave device, so the sclk, sdin and cs signals must be sourced by the application host processor. all read and write access to the device is in itiated and terminated by the application host processor. 4.11.1 cs pin the chip select pin (cs ) is an active-low si gnal provided by the host processor to the GS3140. the high-to-low transition of this pin marks the start of serial communication to the GS3140. the low-to-high transition of this pin mark s the end of serial communication to the GS3140. there is an option for each device to use a separate unique chip select signal from the host processor or for up to 32 devices to be connected to a single chip select when making use of the unit address feature. only those devices whose unit address matches the unit address in the gspi command word will respond to communicat ion from the host processor (unless the bcast all bit in the gspi command word is set to 1). GS3140 final data sheet rev.1 pds-060939 may 2015 20 of 40 semtech proprietary & confidential www.semtech.com 4.11.2 sdin pin the sdin pin is the gspi serial data input pin of the GS3140. 16-bit command and data words from the host processor or from the sdout pin of other devices are shifted into the device on the rising edge of sclk when the cs pin is low. 4.11.3 sdout pin the sdout pin is the gspi serial data output of the GS3140. all data transfers out of the GS3140 to the host processor or to the sdin pin of other connected devices occur from this pin. by default at power up or after system reset, the sdout pin provides a non-clocked path directly from the sdin pin, regardless of the cs pin state, except during the gspi data word portion for read operations to the de vice. this allows multiple devices to be connected in loop-through configuration. for read operations, the sdout pin is used to output data read from an internal configuration and status register (csr) when cs is low. data is shifted out of the device on the falling edge of sclk, so that it can be read by the host processor or other downstream connected device on th e subsequent sclk rising edge. 4.11.3.1 gspi link disable operation it is possible to disable the direct sdin to sdout (loop-through) connection by writing a value of 1 to the gspi_link_disable bit in host_conf_reg_0. when disabled, any data appearing at the sdin pin will not appe ar at the sdout pin and the sdout pin is high. note: disabling the loop-through operation is temporarily required when initializing the unit address for up to 32 connected devices. the time required to enable/disable the lo op-through operation from assertion of the register bit is less than the gspi config uration command delay as defined by the parameter t cmd_gspi_config (4 sclk cycles). table 4-4: gspi_link_disable bit operation bit state description 0 sdin pin is looped through to the sdout pin 1 data appearing at sdin does not appear at sdout, and sdout pin is high. GS3140 final data sheet rev.1 pds-060939 may 2015 21 of 40 semtech proprietary & confidential www.semtech.com figure 4-4: gspi_link_disable operation 4.11.3.2 gspi bus-th rough operation using gspi bus-through operation, the GS3140 can share a common pcb trace with other gspi devices for sdout output. when configured for bus-through operation, by setting the gspi_bus_through_enable bit to 1, the sdout pin will be high-impedance when the cs pin is high. when the cs pin is low, the sdout pin will be driven and will follow regular read and write operation as described in section 4.11.3 . multiple chains of GS3140 devices can share a single sdout bus connection to host by configuring the devices for bus-through operation. in such configuration, each chain requires a separate chip select (cs ). figure 4-5: gspi_bus_through_enable operation sdin pin sdout pin gspi_link _disable bus_through high-z cs pin configuration and status register tae - gspi_bus_throu gh_enable bit operation bit state desription 0 disables bus-through operation 1 enables bus-through operation when cs is high, the sdout pin will be high impedance. when cs is low, the sdout pin is driven. sdin pin sdout pin gspi_link _disable bus_through high-z cs pin configuration and status register GS3140 final data sheet rev.1 pds-060939 may 2015 22 of 40 semtech proprietary & confidential www.semtech.com 4.11.4 sclk pin the sclk pin is the gspi serial data shift cl ock input to the device, and must be provided by the host processor. serial data is clocked into the GS3140 sdin pin on the rising edge of sclk. serial data is clocked out of the device fr om the sdout pin on the falling edge of sclk (read operation). sclk is ignored when cs is high. the maximum interface clock rate is 32mhz. 4.11.5 command word description all gspi accesses are a minimum of 32 bits in length (a 16-bit command word followed by a 16-bit data word) and the start of ea ch access is indicated by the high-to-low transition of the chip select (cs ) pin of the GS3140. the format of the command word and data words are shown in figure 4-6 . data received immediatel y following this high-to-low tran sition will be interpreted as a new command word. 4.11.5.1 r/ w bit - b15 command word this bit indicates a read or write operation. when r/w is set to 1, a read operation is indica ted, and data is read from the register specified by the address field of the command word. when r/w is set to 0, a write operation is indica ted, and data specified in the data word is written to the register specified by the address field of the command word. 4.11.5.2 b'cast all - b14 command word this bit is used in write operations to co nfigure all devices conn ected in loop-through and bus-through configuratio n with a single command. when bcast all is set to 1, the followin g data word (autoinc = 0) or data words (autoinc = 1) are written to the register specified by the address field of the command word (and subsequent addresses when autoinc = 1), regardless of the setting of the unit address(es). when bcast all is set to 0, a normal writ e operation is indicate d. only those devices that have a unit address ma tching the unit address fiel d of the command word write the data word to the regist er specified by the address field of the command word. bcast all must be set to 0 for read operations. 4.11.5.3 emem - b13 command word the emem bit should be set to 0 when acce ssing GS3140. accesses to other devices (unit address field in the command word does not match the device_unit_address in host_conf_reg_0) with emem bit set to 1 are allowed. GS3140 final data sheet rev.1 pds-060939 may 2015 23 of 40 semtech proprietary & confidential www.semtech.com 4.11.5.4 autoinc - b12 command word when autoinc is set to 1, auto-increment read or write access is enabled. in auto increment mode, the device automaticall y increments the register address for each contiguous read or write access, starti ng from the address de fined in the address field of the command word. the internal address is incr emented for each 16-bit read or write access until a low-to-high transi tion on the cs pin is detected. when autoinc is set to 0, single read or write access is required. auto-increment write must not be used to update values in host_conf_reg_0. 4.11.5.5 unit address - b11:b7 command word the 5 bits of the unit address field of the command word are used to select one of 32 devices connected on a single chip select in loop-through or bus-through configurations. read and write accesses are only accepted if the unit address field matches the programmed device_unit_a ddress in host_conf_reg_0 by default at power-up or after a device re set, the device_unit_address is set to 00 h 4.11.5.6 address - b6:b0 command word the 7 bits of the address field are used to select one of the register addresses in the device in single read or write access mode, or to set the starti ng address for read or write accesses in auto-i ncrement mode. figure 4-6: command and data word format msb lsb r / w emem autoinc a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a11 a10 command word unit address address bcast all d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 data word 7-bit csr address field providing up to 128 configuration registers. auto increment read/ write access when set. single read write access when reset. extended memory mode. when set, the extended memory mode is enabled. when reset, normal gspi addressing is enabled (emem is not enabled in the GS3140). read access when this bit is set. write access when this bit is reset. when set, the unit address field is ignored and all data accesses are actioned by the device. when reset, the unit address is used to manage data accesses in the device. 5-bit unit address field providing up to 32 devices to be connected on a single cs. GS3140 final data sheet rev.1 pds-060939 may 2015 24 of 40 semtech proprietary & confidential www.semtech.com 4.11.6 gspi transaction timing figure 4-7: gspi external interface timing r/w bcst sclk write mode sdi signal is looped out on sdo sdout emem auto_inc a4 a3 a2 a1 a0 r/w rsv read mode sdi signal is looped out on sdo emem auto_inc a4 a3 a2 a1 a0 read data is output on sdo d0 r/w bcst sdin emem auto_inc ua 4 ua 3 ua 2 ua 1 ua 0 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 r/w rsv emem auto_inc a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d15 d14 d13 d12 d11 d10 d9 d8 t 0 t 8 t 2 t 3 t 1 t 9 t 6 t 5 t 7 t 4 a6 a5 ua 4 ua 3 ua 2 ua 1 ua 0 a6 a5 ua4ua3ua2ua1ua0 a6 a5 ua 4 ua 3 ua 2 ua 1 ua 0 a6 a5 sclk sdout sdin x t cmd_gspi_config t cmd t 9 sclk sdout sdin x cs cs cs table 4-6 gspi timing parameters parameter symbol euivalent sclk cycles min typ max units sclk frequency 32 mhz cs low before sclk rising edge t 0 1.3 ns sclk period t 1 31.25 ns sclk duty cycle t 2 40 50 60 % input data setup time t 3 1.1 ns sclk idle time -write t 4 1 31.25 1 ns sclk idle time - read t 5 4114ns inter-command delay time t cmd 385 inter-command delay time (after gspi configuration write) t cmd_gspi_conf 2 4114ns GS3140 final data sheet rev.1 pds-060939 may 2015 25 of 40 semtech proprietary & confidential www.semtech.com 4.11.7 single read/write access single read/write access timing fo r the gspi interface is shown in figure 4-8 to figure 4-12 . when performing a single read or write access, one data word is read from/written to the device per access. each access is a mi nimum of 32-bits long, consisting of a command word and a single data word. the read or write cycle begins with a high-to-low transition of the cs pin. the read or write access is terminated by a low-to-high transi tion of the cs pin. the maximum interface clock rate is 32 mhz and the inter-command delay time indicated in the figures as t cmd , is a minimum of 3 sclk clock cycles. after modifying values in host_conf_reg_0, the inter-command delay time, t cmd_gspi_config , is a minimum of 4 sclk clock cycles. for read access, the time from the last bit of the command word to the start of the data output, as defined by t 5 , corresponds to no less than 4 sclk clock cycles at 32mhz. sdo after sclk falling edge t 6 1.9 7.5 ns cs high after final sclk falling edge t 7 0ns input data hold time t 8 1ns cs high time t 9 46.9 ns sdin to sdout combinatorial delay 5 ns max. chips daisy chained at max sclk frequency (32 mhz) when host clocks in sdout data on rising edge of sclk 1 GS3140 chips max. frequency for 32 daisy-chained devices 2.1mhz max. chips daisy-chained at max. sclk frequency (32 mhz) when host clocks in sdout data on falling edge of sclk 3 GS3140 chips max. frequency for 32 daisy-chained devices 2.2mhz notes: 1. parameter is an exact multiple of sclk periods and scales proportionally 2. t cmd_gspi_conf inter-command delay must be used whenever modifying host_conf_reg_0 register at address 0x00 table 4-6: gspi timing parameters (continued) parameter symbol equivalent sclk cycles min typ max units GS3140 final data sheet rev.1 pds-060939 may 2015 26 of 40 semtech proprietary & confidential www.semtech.com figure 4-8: gspi write timing C single write access with l oop-through operation (default) figure 4-9: gspi write timing C single writ e access with gspi link-disable operation figure 4-10: gspi write timing C single write access with bus-through operation figure 4-11: gspi read timing C single read access with loop-through operation (default) figure 4-12: gspi read timing C single read access with bus-through operation sclk cs sdin sdout command command data data command command x x cmd t sclk cs sdin sdout command data command x cmd t sclk cs sdin sdout command command data data command command x high-z cmd t high-z sclk cs sdin sdout command command data 5 t x sclk cs sdin sdout command command data 5 t x high-z high-z GS3140 final data sheet rev.1 pds-060939 may 2015 27 of 40 semtech proprietary & confidential www.semtech.com 4.11.8 auto-increment read/write access auto-increment read/write access timing for the gspi interface is shown in figure 4-13 to figure 4-17 . auto-increment mode is enab led by the setting of the autoinc bit of the command word. in this mode, multiple data words can be read from/written to th e device using only one starting address. each access is initiated by a high-to-low transition of the cs pin, and consists of a command word and one or more data words. the internal address is automatically incremen ted after the first read or writ e data word, and continues to increment until the read or wr ite access is terminated by a low-to-high transition of the cs pin. note: writing to host_conf_reg_0 using au to-increment access is not allowed. the maximum interface clock rate is 32 mhz and the inter-command delay time indicated in the diagram as t cmd , is a minimum of 3 sclk clock cycles. for read access, the time from the last bit of the first command word to the start of the data output of the first data word as defined by t 5 , will be no less than 4 sclk cycles at 32mhz. all subsequent read da ta accesses will not be subjec t to this delay during an auto-increment read. figure 4-13: gspi write timing C auto-incre ment with loop-through operation (default) figure 4-14: gspi write timing C auto-inc rement with gspi li nk disable operation figure 4-15: gspi write ti ming C auto-increment with bus-through operation sclk cs sdin sdout command command data 1 data 1 data 2 data 2 sclk cs sdin sdout command data 1 data 2 sclk cs sdin sdout command command data 1 data 1 data 2 data 2 high-z GS3140 final data sheet rev.1 pds-060939 may 2015 28 of 40 semtech proprietary & confidential www.semtech.com figure 4-16: gspi read timing C auto-increme nt read with loop-thr ough operation (default) figure 4-17: gspi read timing C auto-inc rement read with bu s-through operation 4.11.9 default gspi operation by default at power up or after a device re set, the GS3140 is set for loop-through operation and the internal device_unit_a ddress field of the device is set to 0. figure 4-18 shows a functional block diagram of th e configuration and status register (csr) map in the GS3140. figure 4-18: internal register map functional block diagram the steps required for the application host processor to write to the configuration and status registers via the gspi, are as follows: 1. set command word for write access (r/ w = 0) and desired local address (register address); set auto increment; set the unit address field in the command word to match the configured device_unit_address which will be zero. write the command word. 2. write the data word to be written to the first addressed register. 3. write the data word to be written to the next register in auto increment mode, etc. sclk cs sdin sdout 5 t command command data 1 data 2 x sclk cs sdin sdout 5 t command command data 1 data 2 high-z x [12] [6:0] reg 0 compare configuration and status registers read/write reg 1 reg n cmd at power-up or after a device reset, device_unit_address = 00 h data to be written / read data data [15:0] [11:7] [13] [14] bits local address r / w unit address bcast all auto inc emem [15] device_unit_address gspi_link _disable gspi_bus_ through _enable reserved bits [4:0] [13] [14] [15] 32 devices bits reserved [12:5] GS3140 final data sheet rev.1 pds-060939 may 2015 29 of 40 semtech proprietary & confidential www.semtech.com read access is the same as the above except in step 1 the command word is set for read access (r/w = 1). note: the unit address field of the command word must always match device_unit_address for an access to be accepted by the device. changing device_unit_address to a value other than 0 is only required if multiple devices are connected to a single chip select (in lo op-through or bus-through configuration). 4.11.10 setting a device unit address multiple (up to 32) GS3140 devices can be connected to a common chip select (cs ) in loop-through or bus-through operation. to ensure that each device selected by a common cs can be separate ly addressed, a unique unit address must be programmed by the host proce ssor at start-up as part of system initialization or following a device reset. note: by default at power up or after a devic e reset, the device_unit_address of each device is set to 0h and the sdin sdout non-clocked loop-through for each device is enabled. these are the steps required to set the device_unit_address of devices in a chain to values other than 0: 1. write to unit address 0 selecting host_conf_reg_0 (address = 0), with the gspi_link_disable bit set to 1 and the de vice_unit_address field set to 0. this disables the direct sdin sdout non-clocked path for all devices on chip select. 2. write to unit address 0 selecting host_conf_reg_0 (address = 0), with the gspi_link_disable bit set to 0 and th e device_unit_address field set to a unique unit address. this configures de vice_unit_address for the first device in the chain. each subsequent such write to unit address 0 will configure the next device in the chain. if there are 32 devices in a chain, the last (32nd) device in the chain must use device_unit_address value 0. 3. repeat step 2 using new, unique valu es for the device_unit_address field in host_conf_reg_0 until all devices in the chain have been configured with their own unique unit address value. note: t cmd_gspi_conf delay must be observed after every write that modifies host_config_reg_0. all connected devices receive this command (by default the unit address of all devices is 0), and the loop-through operation will be re-established for all connected devices. once configured, each device will only re spond to command words with a unit address field matching the device _unit_address in host_conf_reg_0 note: although the loop-through and bus-through configurations are compatible with previous generation gspi enabled devic es (backward compatibility), only devices supporting unit addressing can share a chip select. all devices on any single chip select must be connected in a contiguous chain with only the last device's sdout connected to the application host processor. multiple chains configured in bus-through mode can have their final sdout outputs connected to a single application host processor input. GS3140 final data sheet rev.1 pds-060939 may 2015 30 of 40 semtech proprietary & confidential www.semtech.com 5. host interface register map table 5-1: register descriptions address register name parameter name bit slice r/w reset description 0 h host_conf_reg_0 rsvd 15:15 rw 0 h reserved. do not change. gspi_link_disable 14:14 rw 0 h gspi loop-through disable. gspi_bus_through_enable 13:13 rw 0 h gspi bus-through enable. rsvd 12:5 rw 0 h reserved. do not change. device_unit_address 4:0 rw 0 h device address programmed by application. 1 h eq_conf_reg_0 rsvd 15:9 rw 0 h reserved. do not change. max_cable_length_config 8:7 rw 3 h manually specify maximum cable length: 00 b = 100m 01 b = 200m 10 b = 300m 11 b = 600m auto_bypass 6:6 rw 0 h enable automatic assertion of bypass (equivalent to bypass=1) when an input signal is detected with a rate below madi. bypass 5:5 rw 0 h forces the equalizer core and dc-restore into bypass mode when set to 1. no equalization occurs in this mode. rsvd 4:4 rw 0 h reserved. do not change. custom_dyn_pwr_mode 3:3 rw 0 h enable dynamic power mode. control bit overrides default when custom_dyn_pwr_mode_ enable is set to 1. custom_dyn_pwr_mode_ enable 2:2 rw 0 h when set to 1, overrides the dynamic power mode with value specified by parameter custom_dyn_pwr_mode. when set to 0 dynamic power mode will default to disabled. sleep 1:0 rw 0 h 00 b = normal 01 b = auto-sleep 10 b , 11 b = forced-sleep GS3140 final data sheet rev.1 pds-060939 may 2015 31 of 40 semtech proprietary & confidential www.semtech.com 2 h eq_conf_reg_1 rsvd 15:12 rw 0 h reserved. do not change. sdi_data_rate_value 11:9 rw 0 h when enabled by force_sdi_data_rate_value. 000 b = force GS3140 final data sheet rev.1 pds-060939 may 2015 33 of 40 semtech proprietary & confidential www.semtech.com 6 h status_reg_0 cable_length_indicator 15:8 ro 0 h an 8 bit number representing cable length in increments of 2.5m 00 h = 0m (minimum value) ef h = ~600m (maximum value) in accordance with table 4-1 . rsvd 7:4 ro reserved. detected_input_rate 3:1 ro 1 h detected input data rate. 000 b = <125mb/s 001 b = 125mb/s 010 b = 270mb/s 011 b = 1.485gb/s 100 b = 2.97gb/s note: all other states are invalid. los 0:0 ro 0 h loss of signal (los) indication. set to 1 when a qualified signal is present at the input to the device, as detailed in section 4.5 . set to 0 when such signal is not detected. 7 h los_filter_conf_ reg_0 los_filter_set_delay 15:8 rw 2 h loss of signal (los) assertion delay, in increments of approximately 25.9s to a maximum of approximately 6.6ms. 00 h = 0ms ff h = 6.6ms los_filter_clear_delay 7:0 rw 1 h loss of signal de-assertion delay, in increments of approximately 6.6ms to a maximum of approximately 1.7s. 00 h = 0s ff h = 1.7s 8 h los_filter_conf_ reg_1 rsvd 15:1 rw 0 h reserved. do not change. los_filter_disable 0:0 rw 0 h disables loss of signal (los) filter as shown in figure 4-1 . table 5-1: register descriptions (continued) address register name parameter name bit slice r/w reset description GS3140 final data sheet rev.1 pds-060939 may 2015 34 of 40 semtech proprietary & confidential www.semtech.com 9 h int_out_conf_ reg_0 rsvd 15:11 rw 0 h reserved. do not change. data_rate_detection 10:6 rw 0 h data rate detection enable. selects which data rates will be reported on the int pin when int_source_select is set to 100 b or 101 b . set the corresponding bit to 1 to enable detection reporting for each rate. bit 0 = < madi bit 1 = madi bit 2 = sd bit 3 = hd bit 4 = 3g int_source_select 5:3 rw 0 h selects the internal signal source for the int pin. 000 b = loss of signal (los), filtered per registers los_filter_conf_reg_0 and los_filter_conf_reg_1 001 b = specific signal presence status as selected by int_cd_mode_select 010 b = reserved 011 b = an active-high minimum 200ns pulse generated upon each detected change in the rate. 100 b = cd qualified with rate(s) selected by data_rate_detection bits 101 = same as settings above, with a minimum 200ns low pulse when a rate change is detected 110 b /111 b = reserved int_cd_mode_select 2:0 rw 0 h carrier detect mode, allows int to assert only for selected rate. 000 b = general carrier detect (cd) (any rate) 001 b = cd for below-madi rates 010 b = cd for madi rates 011 b = cd for sd 100 b = cd for hd 101 b = cd for 3g 110 b , 111 b = reserved a h version_id_reg version_id 15:0 ro 0 h readout of chip version_id. table 5-1: register descriptions (continued) address register name parameter name bit slice r/w reset description GS3140 final data sheet rev.1 pds-060939 may 2015 35 of 40 semtech proprietary & confidential www.semtech.com b h misc_conf_reg_0 high_drive 15:15 rw 0 h drive strength control for digital output pins. 0 b = low drive 1 b = high drive rsvd 14:0 rw 0 h reserved. do not change. c h C 7e h reserved rsvd 15:0 ro reserved. 7f h reset_reg_0 reset_control 15:8 rw dd h device reset, reverts all internal logic and register values to defaults. write values: aa h : asserts device reset dd h : de-assert device reset ad h : assert/de-assert device reset in a single write read values: aa h : user-initiated reset is asserted dd h : user-initiated reset is de-asserted rsvd 7:0 rw 0 h reserved. do not change. table 5-1: register descriptions (continued) address register name parameter name bit slice r/w reset description GS3140 final data sheet rev.1 pds-060939 may 2015 36 of 40 semtech proprietary & confidential www.semtech.com 6. application information 6.1 typical application circuit figure 6-1: typical application circuit GS3140 sdi sclk sdin sdout agc vee_a vee_o int ddo vcc_a vcc_o sdi vcc_d cs agc ddo 470nf *value dependent on layout 4.7f 4.7f 10nf vcc_o 10nf 10nf vcc_a 1f 75 4.3nh* sdi 6.2nh* 75 37.5 vcc_d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1f GS3140 final data sheet rev.1 pds-060939 may 2015 37 of 40 semtech proprietary & confidential www.semtech.com 7. package & ordering information 7.1 package dimensions figure 7-1: package dimensions notes: 1. all dimensions are in millimeters 2. solderable pad finish: matte sn 3. dimensions & tolerances conform to asme y14.5m. C 1994 4.00 0.15 4.00 0.15 0.10 0.08 0.10 0.20 ref 0.035+0.015 C0.035 0.65+0.05 C0.00 0.850.05 0.500.10 0.300.05 c0.3 pin 1 id 0.65 0.500.10 0.10 0.05 laser mark for pin 1 identification in this area a a a c c cc c c c b b b 1 4 16 13 12 9 8 5 seating plane top view side view bottom view GS3140 final data sheet rev.1 pds-060939 may 2015 38 of 40 semtech proprietary & confidential www.semtech.com 7.2 packaging data 7.3 recommended pcb footprint figure 7-2: recommended pcb footprint table 7-1: packaging data parameter value package type 4mm x 4mm 16-pin qfnCcol package drawing reference jedec mo-220 moisture sensitivity level 3 junction to air thermal resistance, j-a (at zero airflow) 63.0c/w junction to board thermal resistance, j-b 37.0c/w junction to case thermal resistance, j-c 44.5c/w psi, ? junction-to-top characterization parameter 2.5c/w pb-free and rohs compliant yes 4.60 0.85 0.40 0.65 0.325 2.90 3.75 notes: 1. controlling dimensions are in millimeters 2. square package - dimensions apply in both ?x? and ?y? directions GS3140 final data sheet rev.1 pds-060939 may 2015 39 of 40 semtech proprietary & confidential www.semtech.com 7.4 marking diagram figure 7-3: marking diagram 7.5 solder reflow profiles figure 7-4: maximum pb-free solder reflow profile 7.6 ordering information xxxx - last 4 digits of assembly lot e3 - pb-free & green indicator yyww - date code pin 1 indicator GS3140 yyww xxxxe3 25c 150c 200c 217c 260c 250c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3c/sec max 6c/sec max table 7-2: ordering information part number package temperature range GS3140-ine3 16-pin qfnCcol -40c to +85c important notice information relating to this product and the application or design described herein is believed to be reliable, however such in formation is provided as a guide only and semtech assumes no liability for any errors in this document, or for the application or design des cribed herein. semtech reserves the right to make changes to the product or this document at any time without notice. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. semtech warrants performance of its products to the specifications applicable at the time of sale, and all sales are made in accordance with semtechs standard ter ms and conditions of sale. semtech products are not designed, intended, authorized or warr anted to be suitable for use in life-support applications, devices or systems, or in nuclear applications in which the failure could be reasonably expected to result in personal injury, loss of life or severe property or environmental dama ge. inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damage s and attorney fees which could arise. the semtech name and logo are registered trademarks of the se mtech corporation. all other trademarks and trade names mentioned may be marks and names of semtech or their respective companies. semtec h reserves the right to make changes to, or discontinue any pro ducts described in this document without further notice. semtech makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose. all rights reserved. ? semtech 2015 GS3140 final data sheet rev.1 pds-060939 may 2015 40 of 40 semtech 40 proprietary & confidential contact information semtech corporation 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111, fax: (805) 498-3804 www.semtech.com |
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